january 2011 doc id 18263 rev 1 1/10 AN3318 application note hsp061-4ny8 high speed line pr otection on hdmi 1.4 link introduction this application note presents the hsp061-4ny8 and its capability to pr otect hdmi 1.3 and hdmi 1.4 tmds lines. the hdmi interface is provided for transmitting digital television audiovisual signals from dvd players, set-top- boxes and other source to television sets and other video displays. hsp061-4ny8 has been developed to be compliant with: hdmi version 1.4 standard knowin g the key point is the capab ility to transfer data with a maximum rate of 3.4 gbps per channel without distortion. this leads the hsp061-4ny8 to have a large bandwidth, to pass fast voltage slope and to keep the 100 line impedance, hsp061-4ny8 is used on the tmds line. iec 61000-4-2 level 4 (8 kv contact discharge) www.st.com
location for hsp061-4ny8 AN3318 2/10 doc id 18263 rev 1 1 location for hsp061-4ny8 many pcb parasitic elements may degrade the overall esd performance of a system. the recommendations below are aimed at optimizing esd protection device placement and the pcb layout to reach the best esd performance possible. the layout shown in figure 1 may induce parasitic inductanc es responsible for artificial overvoltages directly applied on the ic to be protected. a very simple calculation shows that for a 8 kv esd surge according to iec61000-4-2, the overvoltage due to parasitic inductances may be really significant, as shown in figure 2 . assuming that each inductance value is 5 nh (corresponds to metal track 5 mm long): then the overvoltage seen by the ic is: this parasitic inductance must be reduced as much as possible by shortening the ground path return to the gnd via. to avoid esd propagation on the pcb, the es d protection must be placed as close as possible to the esd source with the layout given in the datasheet. the layout given in the datasheet reduces parasitic inductance. it is important to connect the connector on one side of the hsp and the tr ansceiver on the other side. the gnd via on both sides must be used. as esd stress can be propagated on both sides of the cable, a protection device on each end of the cable is required. figure 1. non-optimized location for hsp061-4ny8 figure 2. significant overvoltages due to non-optimal location of hsp061-4ny8 ic to protect via to gnd 1 2 4 5 6 8 37 = via to via to gnd gnd via to ic to protect via to gnd v dt di l v ic esd surge is 8 kv with 1 ns rise time, this leads to 38 a/ns gnd layer gnd di dt = 38 a/ns l di dt v = v + ic v = v + 190 v ic
AN3318 location for hsp061-4ny8 doc id 18263 rev 1 3/10 figure 3. protection location on hdmi equipment wire plug board receptacle (connector) source device (i.e., dvd) tx protection cable assembly board receptacle (connector) sink device (display) rx protection
hsp061-4ny8 topology AN3318 4/10 doc id 18263 rev 1 2 hsp061-4ny8 topology hsp061-4ny8 is packaged in qfn-8l (2 mm x 1 mm) to protect four high speed lines (see figure 4 ). this is a flow-through package to get an easy layout and to ensure the 100 differential impedance on hdmi ( figure 5 ). as pcb tracks are no t cut, this offers the possibility to test a board with or without protecti on depending on circui t portion to test. the device is rated v br min = 6 v @ 1 ma with a low typical leakage current of 0.1 na @ 25 c. for further information refer to the product datasheet for hsp061-4ny8. figure 4. hsp061-4ny8 topology figure 5. hsp061-4ny8 pcb footprint i/o 1 i/o 2 gnd i/o 3 i/o 4 internally not connected gnd internally not connected 1 2 4 5 6 8 3 7 400 m 1 2 4 5 6 8 37 via to gnd via to gnd footprint pad pcb tracks
AN3318 characteristics related to hdmi 1.4 doc id 18263 rev 1 5/10 3 characteristics related to hdmi 1.4 protection bandwidth must be large enough to be transparent when a high bit rate is transferred on the line. the equation below give the relationship between lines, pixels, color depth and bit rate per channel: considering the protection device is equivalent to an rc circuit, the relationship between the required cut-off frequency (f c ) and lane data rate is: for instance, with a 3.4 gbps data rate: figure 6 shows the cut-off frequency of the hsp061-4ny8 is 6 ghz which is high enough to manage hdmi signals at 3.4 gbps. figure 6. s21 attenuation measurement table 1. sample characteristics cea video code video format horizontal total pixel per line vertical total lines per frame frame rate (hz) color depth (bits) hdmi data rate (gbps) lane data rate (gbps) 16 1920 x 1080p 2200 1125 60 24 4.46 1.49 30 5.57 1.86 36 6.68 2.23 48 8.91 2.97 lane data rate = (h_total_pixels) (v_total_lines) ?? color_depth ? ? ? ? 3 (frame_rate) 10 8 f = 0.875 (lane data rate) c min f = 0.875 3.4 gbps = 2.98 ghz c min 3.4 gbps 10 mhz 30 mhz 100 mhz 300 mhz 1 ghz 3 ghz -12 -9 -6 -3 0 -12 -9 -6 -3 0 db f (hz) 6 ghz @ -3db
characteristics related to hdmi 1.4 AN3318 6/10 doc id 18263 rev 1 figure 7. differential impedance figure 7 shows the differential impedance measured with the ?time domain reflectometry? method. this method consists of sending a pulse with a short rise time (200 ps between 10% and 90% for hdmi) and to measure the reflected pulse. this gives the impedance of the line along the signal path. the hdmi standard requires 100 15% differential impedance (between 85 and 115 ). as shown on figure 7 , tdr measurement on hsp061-4ny8 gives an impedance between 91 and 100 . these values are in accordance with the hdmi standard. the eye diagrams defined in the hdmi standard are related to bit rate of the signal and to location (source or sink). there are more constr aints on the source side, this is why we have chosen this one on the datasheet. the duration of the eye corresponds to a bit time. this diagram visualizes signal duration, synchronizati on, overshoot and capability of the signal to move from one state to another one. the key point for protection is to be sure there is no slow down effect. figure 8 shows the eye diagram for a 3.4 gbps signal. this measurement is done directly on the hsp061-4ny8 to avoid pcb measurement effects. measurement shows a large safety margin between the eye pattern and the signal. figure 8. eye diagram at 3.4gbps tr = 200 ps (10% - 90%) 12.5 /div z 0diff = 100 vertical : 200 mv / div horizontal : 50 ps / div
AN3318 characteristics related to hdmi 1.4 doc id 18263 rev 1 7/10 figure 9. iec 61000-4-2 response the goal of a protection device is to prot ect against parasitic disturbances. hdmi 1.4 standard specifies a 8 kv contact discharge requirement according to iec 61000-4-2. the test must be performed 5 times with 1 second during each shot. in figure 9 shows the esd measurement when applied to hsp061-4ny8. after a first short spike, the clamping voltage is limited to less than 20 v at 30 ns and less than 10 v at 60 ns instead of 8 kv. there is no ageing phenomenon and the protection remains efficient whatever the number of surges. it is important to keep in mind most of the integrated circuits are esd rated between 500 v and 2 kv (human body model) thanks to internal protection. esd peak voltage v cl @ 30ns v cl @ 60ns +8kv +202v 17v 9v -8kv -194v -18v -9v 50 v / div 20 ns / div 20gs / s
layout considerations AN3318 8/10 doc id 18263 rev 1 4 layout considerations pcb layout must be optimized to take advantage of all performances of the hsp061-4ny8. for esd protection efficiency, the hsp061-4ny 8 must be located as close as possible to the connector. this will avoid disturbance pr opagation to other co mponents through the coupling effect. to avoid the inductance effect of pcb tracks, it is required to go directly from the connector to the hsp061-4ny8 and then after to go to the hdmi circuit. vias to connect the ground pin of hsp061-4ny8 to the ground plane must be as many as possible and placed as close as possible to the protection device to reduce parasitic inductance on the ground return path. vias to connect ground plane and the connector can be located on both sides of the connector. to be compliant with hdmi requirements, differential pairs must be designed with 100 differential impedance from the connector to the ic. the length of each line in the same differential pair must be equal to minimize intra pair skew. length of lines in different differential pair must also be as equal as far as possible to minimize inter pair skew. track width must be calculated depending on pcb ch aracteristics (relative permittivity, spacing, number of layers?) figure 10 shows an example of pcb layout for hsp061-4ny8 with an hdmi type a smd connector.. figure 10. layout example for hsp061-4ny8 with hdmi type a smd connector hdmi type a connector 100 differential pairs as short as possible vias to ground as many as possible to reduce ground connection inductance hsp06-4ny8 hsp06-4ny8
AN3318 conclusion doc id 18263 rev 1 9/10 figure 11 shows an example of pcb layout for hsp061-4ny8 with an hdmi type c smd connector figure 11. layout example for hsp061-4ny8 with hdmi type c smd connector 5 conclusion the hsp061-4ny8 is perfectly in line with the iec61000-4-2 requirements and is fully compliant with hdmi 1.4 standards and also with most of the other high speed data lines lines (ethernet, displayport, usb3.0, sata?) 6 revision history hsp061-4ny8 hsp061-4ny8 hdmi type c connector 100 differential pairs vias to ground as many as possibble to reduce ground connection inductance as short as possible table 2. document revision history date revision changes 15-jan-2011 1 initial release.
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